AI Chip

From your model to a product.

Bring our core NPU IP into a product. SeM-V1 is our first chip, designed for Voice functionality.

SeM-V1 package concept in development
SeM-V1 · Package concept · In development

SeM-V1

Our first Voice AI Chip, built around Semunite’s core NPU IP.

SeM-V1 is being developed as an Always-On Voice Agent AI Chip product line, separate from the SUAI test chip.

  • Keyword Spotting (KWS)
  • Wake-Word Detection
  • Speech-to-Text (STT)
SeM-V1 package concept and FPGA evaluation platforms
The image shows the SeM-V1 package concept and evaluation platforms. It does not represent finished SeM-V1 silicon or final specifications.

SeM-V1 chip architecture

The full architecture of SeM-V1, our first Voice chip. Four NPU cores connect to a RISC-V Data Core, shared L2 SRAM and peripherals. The data path inside each NPU core is shown separately below.

Explore SeM-V1 architecture and NPU PPA
SeM-V1 chip architecture, including the NPU subsystem, RISC-V Data Core and peripherals.
SeM-V1 chip architecture, including the NPU subsystem, RISC-V Data Core and peripherals.Open full-size diagram (new tab)Open full-size diagram (new tab)
Explore the SeM-V1 NPU core
The INT8 data path has 1 KB input, 4 KB weight and 1 KB output memory, with three DMAs per core.
The INT8 data path has 1 KB input, 4 KB weight and 1 KB output memory, with three DMAs per core.Open full-size diagram (new tab)Open full-size diagram (new tab)

SeM-V1 configuration and NPU specifications

Compute and integration

NPU cluster
4 NPU cores
PE array / core
32 × 6 INT8
MAC throughput
192 MAC/cycle/core · 768 MAC/cycle
Accumulation
32-bit
SRAM / core
Input 1 KB · Weight 4 KB · Output 1 KB
DMA
3 DMA/core · Input / Weight / Output
Data Core
RISC-V CV32E40P + FPU
Shared L2 SRAM
1 MB
Peak performance
≈ 0.31 TOPS · INT8 · 200 MHz
Interfaces
QSPI, UART, I2C, I2S/PDM, SDIO, GPIO, JTAG
Process / I/O
Samsung 28nm · 3.3 V I/O

Peak performance is specified at INT8 and 200 MHz. The QuartzNet workload throughput is shown separately.

NPU PPA · QuartzNet

Throughput
49 GOPS (INT8)
Power
15.4 mW
Efficiency
3.2 TOPS/W · 0.9 V
Efficiency (est.)
5.0 TOPS/W · Estimated · 0.7 V
Area · 4 cores
0.43 mm²
Conditions
INT8 · 400 MHz / 0.9 V

Synopsys PrimeTime PX results for the NPU block during QuartzNet compute, INT8, 400 MHz / 0.9 V. Area is the sum of four P&R cores including SRAM and DFT. Efficiency at 0.7 V is estimated.

SeM-V1 Development Status

Evaluate product integration against the development and validation status of each product.

SeM-V1
AI Chip development in progress
Power efficiency
Product-specific validation in progress
Compiler · Runtime · Profiling
Deployment software · evaluation hardware

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