CORE NPU IP · PIM-LIKE NPU
PIM-like
NPU
Semunite NPU IP with Zero-skipping
Bring compute and memory closer.
Focus on necessary computation.
Zero-skipping added · Not yet taped out
PIM-like
DATA MOVEMENT BETWEEN COMPUTE AND MEMORY
DATA MOVEMENT
Physical distance between compute and memoryEnergy spent moving data
Workload-specific optimization
PIM-like NPU.
Compute meets memory.
PIM-LIKE NPU DESIGN APPROACH
CLOSER COMPUTE
Manual placement brings compute and memory closerMinimize data movement
Optimize power, performance and area (PPA)
PIM-LIKE NPU IP
PIM-like NPU IP
Semunite’s PIM-like NPU places compute units and memory close together to minimize data movement. We have enhanced the NPU IP with Zero-skipping to skip unnecessary computations involving zero values.
- Manual physical designPlace compute and memory close together to minimize data movement
- PPA optimizationReduce energy consumption, computation time and chip area together
- Zero-skippingAdded support for skipping unnecessary computations involving zero values
Zero-skipping added · Not yet taped out
The updated IP is planned for integration into a future VUI AI Chip tape-out.
SeM-V1 · NPU PPA · QuartzNet
49 GOPS · 15.4 mWINT8 · 4 NPU cores · 400 MHz / 0.9 V · Synopsys PrimeTime PX
NPU block · 0.43 mm² · 3.2 TOPS/W at 0.9 V. Efficiency of 5.0 TOPS/W at 0.7 V is estimated.
Read the CEO interview on technology and validation
The next directions for NPU IP
We are preparing NPU IP extensions for SLM and Vision.
PRODUCT DETAIL · VUI EDGE AI
SeM-V1
Our first Voice AI Chip, built around Semunite’s core NPU IP.
A low-power on-device Voice AI Chip development system for KWS, wake-word detection, and STT workloads, including compiler, runtime, profiling, and evaluation hardware.
- Keyword Spotting (KWS)
- Wake-Word Detection
- Speech-to-Text (STT)
- Compiler · Runtime · Profiling
Platform · From model integration to system evaluation
- SDK & Compiler
AI model analysis and NPU mapping
- Runtime & Profiling
Execution environment and performance analysis
- Evaluation Boards
Hardware validation and system integration
- AI Solutions
Application software and product integration
Always-On Voice Monitoring
Execution path designed for continuous keyword and wake-word detection
Energy-Efficient Inference
Clustered compute and local SRAM reduce data movement
On-Device Execution
KWS, wake word, and STT run on the local device path
PRODUCT LINES
Choose a product line.
01 / 05
SEM PRODUCT · IN DEVELOPMENT
SeM-V1 Development Status
- SeM-V1AI Chip development in progress
- Power efficiencyProduct-specific validation in progress
- 3 Voice WorkloadsKWS · Wake Word · STT
- Compiler · Runtime · ProfilingDeployment software · evaluation hardware
- 7 Patent ApplicationsKorean applications · pending
The image shows the SeM-V1 package concept and evaluation platforms. It does not represent finished SeM-V1 silicon or final specifications.
PRODUCT 02 · SeM-V2
Coming Soon
Product architecture, target workloads, and performance specifications will be disclosed with the development schedule.
PRODUCT 03 · SeM-V3
Coming Soon
Product architecture, target workloads, and performance specifications will be disclosed with the development schedule.
PRODUCT 04 · SeM-N1
Coming Soon
Product architecture, target workloads, and performance specifications will be disclosed with the development schedule.
SUAI LINE · TEST SILICON
SUAI Test Chip
A test chip built to move Semunite’s PIM-like NPU architecture into physical hardware validation.
- Product lineSUAI research silicon
- Tape-outCompleted 2026.01
- Physical siliconSecured 2026.06.22
- ArchitecturePIM-like NPU test implementation
- PurposeArchitecture and hardware validation
SUAI is a test-chip line separate from SeM-V1. The photographed device is not SeM-V1 and does not represent final SeM-V1 commercial specifications.
From design to product. One team.
We connect semiconductor design, software and commercialization to build your next product together.
Meet Semunite
Watch on YouTubeOur milestones
View our historyFirst AI Chip tape-out
The first AI Chip was taped out on Samsung Foundry’s 28 nm process. Further product milestones will be shared as development progresses.
Related interview (new tab)SUAI NPU test silicon secured
Received physical SUAI test chips in June 2026 following tape-out in January 2026. SUAI is a PIM-like NPU test chip, distinct from the SeM-V1 product.
Selected for DIPS
Selected for the DIPS deep-tech startup program, supporting further semiconductor R&D and commercialization.
Semunite in the news
All storiesSOSLAB and Semunite sign MOU for LiDAR and AI semiconductor collaboration (new tab)
The companies plan to combine SOSLAB’s LiDAR and Semunite’s AI semiconductor technologies to explore applications in autonomous mobility, smart infrastructure and robotics, alongside joint demonstrations, R&D and business expansion.
Semunite’s NPU and AI Chip vision: a conversation with CEO Sangyeob Kim (new tab)
The thinking behind Semunite, its PIM-like NPU, and the path toward on-device AI products.
Brain-inspired AI chip enables low-power LLM processing (new tab)
Research on a complementary transformer involving Sangyeob Kim at KAIST, before Semunite was founded.
NPU IP · Model Evaluation
Review NPU design around your model’s operators, memory footprint and latency targets.
Request Model EvaluationAI Chip · Platform Partnerships
Define silicon and platform integration around your product, interfaces, power and area requirements.
Discuss System Integration