Semunite’s PIM-like NPU places compute units and memory close together to minimize data movement. We have enhanced the NPU IP with Zero-skipping to skip unnecessary computations involving zero values.
Zero-skipping added · Not yet taped out
PIM-like NPU IP is Semunite’s core technology. Compute and memory are placed close together, with compute, data movement and memory configured around the model.
A complementary architecture combining the low-power characteristics of PIM (Processing-in-Memory) with the high reconfigurability of an NPU. Rather than relying solely on automated EDA placement and routing, we use manual physical design to place compute units and memory close together. Minimizing data movement reduces energy consumption, computation time and chip area through PPA optimization.
SeM-V1 is the first chip built around this core NPU IP, designed for Voice functionality.
Explore SeM-V1 architecture and specificationsWe have added a function to the NPU IP that skips unnecessary computations involving zero values.
Zero-skipping added · Not yet taped out
The updated IP is planned for integration into a future VUI AI Chip tape-out.
VUI AI Chip integration · Future tape-out
PIM-like NPU test chip
SUAI was taped out in January 2026, and physical chips were received in June 2026.
Peak performance for all 32 cores at 200 MHz. INT8 computation uses four serial passes through the INT4 array.
Per-core peak values for the PIM-like array block, excluding I/O SRAM. Synopsys PrimeTime PX on a P&R netlist with gate-level simulation activity, 200 MHz, SS 0.9 V / −40 °C, 100% MAC utilization, no SPEF parasitics.
An example AI SDK flow for applying the NPU IP in SeM-V1. It analyzes TFLite INT8 models and connects NPU and RISC-V execution.
Prepare a TFLite INT8 model
Analyze layers and quantization, split NPU/RISC-V work and schedule four cores
NPU/DMA drivers, audio pre-processing and host protocol
Build ELF with RISC-V GCC
Place ELF and weights in QSPI Flash
We are preparing NPU IP extensions for SLM and Vision.
Memory architecture and compute optimization for running small language models on device.
The direction includes flash weight streaming, HyperRAM KV cache, weight compression and speculative decoding.
Multi-core compute and memory/data-path extensions for compact vision models.
The direction includes CNN/ViT dataflow, shared L2 and tiling, HyperRAM and a camera interface.
These are future development targets to be refined around the model, quantization, memory and operating conditions. Current NPU validation figures appear separately in the SUAI section.
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